1. Field of the Invention
This invention relates generally to the field of computer systems and, more particularly, to encoded signals within computer systems.
2. Description of the Related Art
Computer systems typically include one or more clock signals. The clock signals are provided to a myriad of devices in the computer system in order to synchronize the operation of the system. Once a clock signal is generated within a computer system, it needs to be distributed to each device in the computer system that uses the clock signal. Clock signals are generally distributed using physical connections on printed circuit boards (pcb's) to pin connections on IS integrated circuits. A clock signal may require a clock fanout buffer to generate sufficient power to distribute the clock signal throughout the system. This infrastructure required to support a clock distribution can be referred to as a clock distribution domain. Infrastructure costs can become high when a large number of devices is introduced into a computer system.
Computer systems may include a large number of devices that require multiple clock signals. These devices may require multiple clock signals where the signals operate at different frequencies. In traditional systems, additional clock distribution domains are included to generate a distribute the additional clock signal to the devices. The additional clock distribution domains can introduce additional infrastructure costs into the computer system. The additional costs become particularly troublesome in computer systems that support a large number of devices. A system is needed that can distribute multiple clock signals to multiple devices while minimizing the clock infrastructure needed to support multiple clock domains.
The problems outlined above are in large part solved by the use the apparatus and method described herein. Generally speaking, an apparatus and method for distributing multiple clock signals to multiple devices using an encoded clock signal is provided. A source clock signal can be encoded to result in an encoded system clock. The encoded system clock can be distributed to multiple devices in a computer system. The devices can decode the encoded system clock signal to generate a system clock signal and a global clock signal. The system clock signal and the global clock signal can then be distributed to their respective clock loads on each device. In certain embodiments, additional information, such as state information, can be encoded into the encoded system clock. A device can be configured to decode the additional information and can alter its state accordingly.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.